As is well known in the microelectronics industry, integrated circuit devices may be susceptible to damage from application of excessive voltages, such as, for example, electrostatic discharge (ESD) events. In particular, during an ESD event, charge transferred within a circuit may develop voltages that are large enough to break down insulating films (e.g., gate oxides) on the device or dissipate sufficient energy to cause electrothermal failures in the device. Such failures may include contact spiking, silicon melting, or metal interconnect melting. As such, protection circuits are often connected to I/O bonding pads of an integrated circuit to safely dissipate energy associated with ESD events away from active circuitry. Protection circuits may also be connected to power supply pads or between power supply buses to prevent damage to active circuitry. In developing effective ESD protection circuitry, circuit designers may, however, be limited with regard to the particular structures used, since the protection circuit will often be closely associated with the remainder of the integrated circuit. For instance, integrated circuits which operate with applications of high voltages (e.g., VDD>12 volts) may include protection circuitry configured to accommodate high voltage levels.